Module] direct mode tx data last fifo – Digi NS9215 User Manual
Page 383
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I / O H U B M O D U L E
[Module] Direct Mode TX Data Last FIFO
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383
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
[ M o d u l e ] D i r e c t M o d e T X D a t a L a s t F I F O
Addresses: 9000_002C / 9000_802C / 9001_002C /9001_802C / 9002_002C /
9000_802C / 9003_002C
The Direct Mode TX Data LAst FIFO register is used when in direct mode of
operation, to write to the TX data FIFO and to cause a last status flag to be set for
use by the peripheral. The write can be 8-, 16-, or 32-bit.
Register
Register bit
assignment
Bit(s)
Access
Mnemonic
Reset
Description
D31:00
W
TXD
0x0
TX Data FIFO Write register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
TXDL
TXDL
Bit(s)
Access
Mnemonic
Reset
Description
D31:00
W
TXDL
0x0
TX Data with Last Status FIFO Write register.