Digi NS9215 - Manual (Page 22)

22 Hardware Reference NS9215
SPI module structure ..................................................................434
SPI controller..................................................................................434
Simple parallel/serial data conversion .............................................434
Full duplex operation .................................................................434
SPI clocking modes ...........................................................................435
Timing modes ..........................................................................435
Clocking mode diagrams..............................................................435
SPI clock generation..........................................................................436
Clock generation samples ............................................................436
In SPI master mode ....................................................................436
In SPI slave mode ......................................................................436
System boot-over-SPI operation............................................................436
Available strapping options ..........................................................437
EEPROM/FLASH header ...............................................................437
Header format .........................................................................437
Time to completion ...................................................................438
SPI Control and Status registers ............................................................439
Register address map .................................................................439
SPI Configuration register ...................................................................439
Clock Generation register ...................................................................440
Register programming steps .........................................................441
Interrupt Enable register ....................................................................441
Interrupt Status register.....................................................................442
SPI timing characteristics ...................................................................443
SPI master timing diagram ...........................................................444
SPI slave timing parameters .........................................................444
SPI slave timing diagram..............................................................445
C h a p t e r 1 3 : I 2 C M a s t e r / S l a v e I n t e r f a c e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 7
Overview ................................................................................447
Physical I2C bus ...............................................................................447
Multi-master bus .......................................................................448
I2C external addresses.......................................................................448
I2C command interface ......................................................................449
Locked interrupt driven mode .......................................................449
Master module and slave module commands......................................449
Bus arbitration .........................................................................449
I2C registers ...................................................................................450
Register address map .................................................................450
Command Transmit Data register ..........................................................450
Register .................................................................................450
Register bit assignment...............................................................451
Status Receive Data register................................................................451
Register .................................................................................451