Digi NS9215 - Manual (Page 434)

S E R I A L C O N T R O L M O D U L E : S P I
SPI controller
434 Hardware Reference NS9215
SPI module
structure
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S P I c o n t r o l l e r
The SPI controller provides a full-duplex, synchronous, character-oriented data
channel between master and slave devices, using a four-wire interface (RXD, TXD,
CLK, CS#). The master interface operates in a broadcast mode. The slave interface
is activated using the CS# signal. You can configure the master interface to address
various slave interfaces using the GPIO pins.
Simple
parallel/serial
data conversion
SPI provides simple parallel/serial data conversion to stream serial data between
memory and a peripheral. The SPI port has no protocol associated with it other than
transferring information in multiples of 8 bits.
Full duplex
operation
The SPI port can operate in full-duplex mode. Information transfer is controlled by a
single clock signal. The clock and chip select signals are chip outputs for a master
mode operation and inputs for a slave mode operation.
Config
AHB Bus
va
li
d
be
[1
:0
]
d
a
ta
[3
1:
0]
re
a
d
wr
it
e
be
[1
:0
]
d
a
ta
[3
1:
0]
s
ta
tu
s
[6
:0
]
sys_pll_out spi_clk
sp
i_
c
lk_o
u
t
sp
i_
tx
_
d
s
p
i_
c
s
_
out
_
n
s
p
i_
cs
_
in_n
s
p
i_
cs
_
in_n
sp
i_
rx
_
d
sp
i_
c
lk
_
in
spi_tx_d
spi_clk_out
spi_cs_out_n
sp
i_
ir
q
Transmit
State
Machine
Receive
State
Machine
Clock
Generation
Transmit
Fifo
Interface
Receive
Fifo
Interface