Digi NS9215 - Manual (Page 280)

E T H E R N E T C O M M U N I C A T I O N M O D U L E
Ethernet General Control Register #1
280 Hardware Reference NS9215
Register bit
assignment
Bits Access Mnemonic Reset Description
D31 R/W ERX 0 Enable RX packet processing
0
Reset RX
1 Enable RX
Used as a soft reset for the RX. When cleared, resets all
logic in the RX and flushes the FIFO.
The ERX bit must be set active high to allow data to be
received from the MAC receiver.
D30 R/W ERXDMA 0 Enable receive DMA
0
Disable receive DMA data request (use to stall
receiver)
1 Enable receive DMA data request
Must be set active high to allow the RX_RD logic to request
the AHB bus to DMA receive frames into system memory.
Set this bit to zero to temporarily stall the receive side
Ethernet DMA. The
RX_RD logic stalls on frame
boundaries.
D29 N/A Reserved N/A N/A
D28 R/W ERXSHT 0 Accept short (<64) receive frames
0 Do not accept short frames
1 Accept short frames
When set, allows frames that are smaller than 64 bytes to
be accepted by the
RX_WR logic.
ERXSHT is typically set for debugging only.
D27:24 R/W Not used 0 Always write as 0.
D23 R/W ETX 0 Enable TX packet processing
0 Reset TX
1 Enable TX
Used as a soft reset for the TX. When cleared resets all
logic in the TX and flushes the FIFOs.
ETX must be set active high to allow data to be sent to the
MAC and to allow processor access to the TX buffer
descriptor RAM.