Master address register, Register – Digi NS9215 User Manual
Page 452
I 2 C M A S T E R / S L A V E I N T E R F A C E
Master Address register
452
Hardware Reference NS9215
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M a s t e r A d d r e s s r e g i s t e r
Address: 9005 0004
If using 7-bit addressing, the master device address field uses only bits D07:01;
otherwise, all 10 bits are used.
Register
D13
R
SCMDL
N/A
Slave command lock
The Slave Command register is locked.
D12
R
MCMDL
N/A
Master command lock
The Master Command register is locked.
D11:08
R
IRQCD
N/A
Interrupt codes
(irq_code
)
The interrupt is cleared if this register is read.
See “Interrupt Codes” on page 455 for more
information.
D07:00
R
RXDATA
N/A
Received data from I
2
C bus
Together with a
RX_DATA
interrupt, this register
provides a received byte (see “Master/slave
interrupt codes” on page 455).
Bits
Access
Mnemonic
Reset
Description
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Master device address
Mstr
addr
mode
Reserved