Digi NS9215 - Manual (Page 359)

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A E S D A T A E N C R Y P T I O N / D E C R Y P T I O N M O D U L E
Decryption
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The DMA channel does not try a transfer when the F bit is clear. The DMA channel
enters an idle state upon fetching a buffer descriptor with the F bit cleared.
When the F bit is modified by the device driver, the device driver must also write an
‘I’ to the CE bit (in the DMA Control register) to activate the idle channel.
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D e c r y p t i o n
During decryption, the expanded key must be fed to the AES core backwards. The
hardware key expander can handle this, but the input key is different than for
encryption. The key must be expanded and the last words must be written to the
key buffer as shown:
A 128-bit key (K0, K1, K2, K3) is expanded to the following 32-bit word
sequence: K0, K1, ..., K40, K41, K42, K43.
To expand the key backwards, the hardware key expander needs K40-K43.
A 192-bit key (K0, K1, K2, K3, K5, K6) is expanded to the following 32-bit word
sequence: K0, K1, ..., K46, K47, K48, K49, K50, K51.
To expand the key backwards, the hardware key expander core needs
K48-51 followed by K46-47.
A 256-bit key (K0, K1, K2, K3, K5, K6, K7) is expanded to the following 32-bit
word sequence: K0, K1, ..., K52, K53, K54, K55, K56, K57, K58, K59.
To expand the key backwards, the hardware key expander core needs
K56-59 followed by K52-55.
The hardware key expander recreates all the remaining words in backwards order.
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E C B p r o c e s s i n g
ECB mode does not require an initialization vector. Software just needs to set up a
key buffer descriptor, followed by a data buffer descriptor.
Processing flow
diagram
This is the ECB buffer descriptor processing flow: