Digi NS9215 - Manual (Page 7)

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ICache and DCache behavior ..........................................................90
R2: Translation Table Base register.........................................................91
Register format..........................................................................91
R3:Domain Access Control register..........................................................91
Register format..........................................................................91
Access permissions and instructions .................................................91
R4 register ......................................................................................92
R5: Fault Status registers.....................................................................92
Access instructions......................................................................92
Register format..........................................................................92
Register bits .............................................................................92
Status and domain fields...............................................................93
R6: Fault Address register ....................................................................93
Access instructions......................................................................93
R7:Cache Operations register ................................................................94
Write instruction ........................................................................94
Cache functions .........................................................................94
Cache operation functions.............................................................95
Modified virtual address format (MVA) ..............................................96
Set/Way format .........................................................................96
Set/Way example .......................................................................96
Test and clean DCache instructions..................................................96
Test, clean, and invalidate DCache instruction ....................................97
R8:TLB Operations register...................................................................97
TLB operations ..........................................................................97
TLB operation instructions ............................................................97
Modified virtual address format (MVA) ..............................................98
R9: Cache Lockdown register ................................................................98
Cache ways...............................................................................98
Instruction or data lockdown register ...............................................99
Access instructions......................................................................99
Modifying the Cache Lockdown register.............................................99
Register format..........................................................................99
Cache Lockdown register L bits.......................................................99
Lockdown cache: Specific loading of addresses into a cache-way ............ 100
Cache unlock procedure ............................................................. 101
R10:TLB Lockdown register ................................................................ 101
Register format........................................................................ 101
P bit ..................................................................................... 101
Invalidate operation .................................................................. 101
Programming instructions............................................................ 102
Sample code sequence ............................................................... 102
R11 and R12 registers ....................................................................... 102
R13:Process ID register ..................................................................... 102
FCSE PID register...................................................................... 103