Digi NS9215 - Manual (Page 50)

P I N O U T ( 2 6 5 )
POR and battery-backed logic
50 Hardware Reference NS9215
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P O R a n d b a t t e r y - b a c k e d l o g i c
The POR will generate keep reset_out_n low between 75ms and 300ms after 3.3V
reaches the POR reference trip voltage threshold. The POR reference trip voltage is
between 2.74V and 2.97V, with hysteresis between 50mV and 80mV.
If the POR feature is not used, and the RTC is used, the inputs must be terminated
as shown below.
Pin Signal U/D I/O OD Description
M3 por_gnd_reg POR reference ground
N2 por_vss POR VSS
P1 por_vdd POR VDD (3.3V)
L3 por_reference POR reference trip voltage (2.74V min /
2.97V max)
T1 por_early_reference POR early power loss voltage (1.19V min /
1.28V max)
N4 bat_vdd Battery VDD (3.0V)
R1 aux_comp Auxiliary analog comparator input (trip point
2.4V min / 2.5V max)
N3, M4 bat_vdd_reg Battery regulated core VDD (1.8V)
P3 por_bypass U I POR bypass, pull low to disable POR
L4 por_test POR analog test pin, leave unconnected
M3 por_gnd_reg tie to ground
N2 por_vss tie to ground
P1 por_vdd tie to 3.3V
L3 por_reference tie to 3.3V
T1 por_early_reference tie to ground
P3 por_bypass tie to 1.8V
E12 reset_n tie to system reset (remains active low 40 ms Min. after 3.3V & 1.8V are valid)
A5 reset_out_n leave open
M13,
M14,
L14 sys_mode [2.0] POR disabled (See System mode table & JTAG drawing following JTAG Test
table)