Digi NS9215 - Manual (Page 19)

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Last (L) bit ............................................................................. 358
Full (F) bit.............................................................................. 358
Decryption .................................................................................... 359
ECB processing ............................................................................... 359
Processing flow diagram ............................................................. 359
CBC, CFB, OFB, and CTR processing ...................................................... 360
Processing flow diagram ............................................................. 360
CCM mode..................................................................................... 360
Nonce buffer........................................................................... 361
Processing flow........................................................................ 361
C h a p t e r 9 : I / O H u b M o d u l e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 3
Block diagram ......................................................................... 364
AHB slave interface................................................................... 364
DMA controller ............................................................................... 364
Servicing RX and FIFOs ............................................................... 364
Buffer descriptors..................................................................... 365
Source address [pointer]............................................................. 365
Buffer length........................................................................... 365
Control[15] – W ........................................................................ 365
Control[14] – I ......................................................................... 365
Control[13] – L......................................................................... 365
Control[12] – F......................................................................... 365
Control[11:0] .......................................................................... 366
Status[15:0] ............................................................................ 366
Transmit DMA example...................................................................... 367
Process.................................................................................. 367
Visual example ........................................................................ 368
Control and status register address maps................................................ 368
UART A register address map ....................................................... 369
UART B register address map ....................................................... 369
UART C register address map ....................................................... 370
UART D register address map ....................................................... 370
SPI register address map............................................................. 371
AD register address map ............................................................. 371
Reserved................................................................................ 371
I2C register address map............................................................. 371
Reserved................................................................................ 371
RTC register address map............................................................ 372
IO Hardware Assist register address map (0) ..................................... 372
IO Hardware Assist register address map (1) ..................................... 372
IO register address map (0) ......................................................... 372
IO register address map (1) ......................................................... 372
[Module] Interrupt and FIFO Status register ............................................. 372