Digi NS9215 - Manual (Page 271)

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E T H E R N E T C O M M U N I C A T I O N M O D U L E
Transmit packet processor
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Transmitting a
frame
Setting the EXTDMA (enable transmit DMA) bit in Ethernet General Control Register
#1 starts the transfer of transmit frames from the system memory to the TX_FIFO.
The
TX_WR logic reads the first buffer descriptor in the TX buffer descriptor RAM.
If the F bit is set, it transfers data from system memory to the TX_FIFO using
the buffer pointer as the starting point. This process continues until the end of
the buffer is reached. The address for each subsequent read of the buffer is
incremented by 32 bytes (that is,
0x20 ). The buffer length field in the buffer
descriptor is decremented by this same value, each transfer, to identify when
the end of the buffer is reached.
If the L field in the buffer descriptor is 0, the next buffer descriptor in the RAM
continues the frame transfer until the L field in the current buffer descriptor is
1. This identifies the current buffer as the last buffer of a transmit frame.
After the entire frame has been written to the TX_FIFO, the TX_WR logic waits for a
signal from the
TX_RD
logic indicating that frame transmission has completed at the
MAC. The TX_WR logic updates the buffer length, status, and F fields of the current
buffer descriptor (that is, the last buffer descriptor for the frame) in the TX buffer
descriptor RAM when the signal is received.
F When set, indicates the buffer is full. The TX_WR logic clears this bit after emptying
a buffer. The system software sets this bit as required, to signal that the buffer is ready
for transmission. If the
TX_WR logic detects that this bit is not set when the buffer
descriptor is read, it does one of two things:
If a frame is not in progress, the TX_WR logic sets the TXIDLE bit in the Ethernet
Interrupt Status register.
If a frame is in progress, the TXBUFNR bit in the Ethernet Interrupt Status
register is set.
In either case, the TX_WR logic stops processing frames until TCLER (clear transmit
logic) in Ethernet General Control Register #2 is toggled from low to high.
TXBUFNR is set only for frames that consist of multiple buffer descriptors and
contain a descriptor — not the first descriptor — that does not have the F bit set after
frame transmission has begun.
Buffer length This is a dual use field:
When the buffer descriptor is read from the TX buffer descriptor RAM, buffer
length indicates the length of the buffer, in bytes. The TX_WR logic uses this
information to identify the end of the buffer. For proper operation of the TX_WR
logic, all transmit frames must be at least 34 bytes in length.
When the TX_WR logic updates the buffer descriptor at the end of the frame, it
writes the length of the frame, in bytes, into this field for the last buffer
descriptor of the frame.
If the MAC is configured to add the CRC to the frame (that is, CRCEN in MAC
Configuration Register #2 is set to 1), this field will include the four bytes of
CRC. This field is set to 0x000 for jumbo frames that are aborted. Only the
lower 11 bits of this field are valid, since the maximum legal frame size for
Ethernet is 1522 bytes.
Field Description