Digi NS9215 - Manual (Page 141)

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S Y S T E M C O N T R O L M O D U L E
Address decoding
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BRC1[23:16] = 8’b1_0_00_0000 channel disabled
BRC1[15:8] = 8’b1_0_00_0000 channel disabled
BRC1[7:0] = 8’b1_0_00_0000 channel disabled
BRC2[31:24] = 8’b0_0_00_0000 channel disabled
BRC2[23:16] = 8’b0_0_00_0000 channel disabled
BRC2[15:8] = 8’b0_0_00_0000 channel disabled
BRC2[7:0] = 8’b0_0_00_0000 channel disabled
BRC3[31:24] = 8’b0_0_00_0000 channel disabled
BRC3[23:16] = 8’b0_0_00_0000 channel disabled
BRC3[15:8] = 8’b0_0_00_0000 channel disabled
BRC[7:0] = 8’b0_0_00_0000 channel disabled
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A d d r e s s d e c o d i n g
A central address decoder provides a select signal — hsel_x — for each slave on the
bus.
This table shows how the system memory address is set up to allow access to the
internal and external resources on the system bus. Note that the external memory
chip select ranges can be reset after powerup. The table shows the default powerup
values; you can change the ranges by writing to the BASE and MASK registers (see
“System Memory Chip Select 0 Dynamic Memory Base and Mask registers” on
page 190 through “System Memory Chip Select 3 Dynamic Memory Base and Mask
registers” on page 193 for more information).
Address range Size System functions
0x0000 0000 – 0x0FFF FFFF 256 MB System memory chip select 0
Dynamic memory (default)
0x1000 0000 – 0x1FFF FFFF 256 MB System memory chip select 1
Dynamic memory (default)
0x2000 0000 – 0x2FFF FFFF 256 MB System memory chip select 2
Dynamic memory (default)
0x3000 0000 – 0x3FFF FFFF 256 MB System memory chip select 3
Dynamic memory (default)
0x4000 0000 – 0x4FFF FFFF 256 MB System memory chip select 0
Static memory (default)
0x5000 0000 – 0x5FFF FFFF 256 MB System memory chip select 1
Static memory (default)
0x6000 0000 – 0x6FFF FFFF 256 MB System memory chip select 2
Static memory (default)