Digi NS9215 User Manual
Page 426
S E R I A L C O N T R O L M O D U L E : H D L C
Interrupt Status register
426
Hardware Reference NS9215
Register
Register bit
assignment
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
TBC
Reserv
ed
Not used
VCRC RABORT
HINT Reserv
ed OFLOW ICRC
RXCLS
RBC TX_IDLERX_IDLE
Bits
Access
Mnemonic
Reset
Description
D31:22
R/W
Not used
0
Write this field to 0.
D21
R/W1TC
HINT
0
HDLC interrupt
Indicates that the HDLC has generated an interrupt.
D20
N/A
Reserved
N/A
N/A
D19
R/W1TC
OFLOW
0
Enable overflow error
Indicates that an overflow occurred in the HDLC’s 4-byte
FIFO.
Note:
This should not happen in a properly configured
system.
D18
R/W1TC
ICRC
0
Invalid CRC
Indicates that a frame has been received with a CRC error.
D17
R/W1TC
VCRC
0
Valid CRC
Indicates that a frame has been received with a valid CRC.
D16
R/W1TC
RABORT
0
Receive abort error
Indicates that a frame has been received with an abort.
D15
N/A
Reserved
N/A
N/A
D14
R/W1TC
RXCLS
0
Software receive close
Indicates a software-initiated buffer close has completed.
D13:04
N/A
Reserved
N/A
N/A
D03
R/W1TC
TBC
0
Transmit buffer close
Indicates that transmission of the last byte in a transmit
buffer has completed.
D02
R/W1TC
RBC
0
Receive buffer close
Indicates that a HDLC receive buffer close condition has
occurred. These are HDLC receive buffer close events:
1
Receive overrun detected
2
Receive abort detected
3
Buffer closed due to invalid CRC
4
Buffer closed due to valid CRC