Digi NS9215 - Manual (Page 135)

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W O R K I N G W I T H T H E C P U
Noncachable instruction fetches
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recommended that either a nonbuffered store ( STR ) or a noncached load
( LDR ) be used to trigger external synchronization.
4
Invalidate the cache. The ICache must be invalidated to remove any stale
copies of instructions that are no longer valid. If the ICache is not being used,
or the modified regions are not in cachable areas of memory, this step might
not be required.
5
Flush the prefetch buffer. To ensure consistency, the prefetch buffer should be
flushed before self-modifying code is executed (see “Self-modifying code” on
page 133).
Sample IMB
sequences
These sequences correspond to steps 1–4 in "IMB operation."
clean loop
MRC p15, 0, r15, c7, c10, 3 ; clean entire dcache using test and clean
BNE clean_loop
MRC p15, 0, r0, c7, c10, 4 ; drain write buffer
STR rx,[ry] ; nonbuffered store to signal L2 world to
; synchronize
MCR p15, 0, r0, c7, c5, 0 ; invalidate icache
This next sequence illustrates an IMB sequence used after modifying a single
instruction (for example, setting a software breakpoint), with no external
synchronization required:
STR rx,[ry] ; store that modifies instruction at address ry
MCR p15, 0, ry, c7, c10, 1 ; clean dcache single entry (MVA)
MCR p15, 0, r0, c7, c10, 4 ; drain write buffer
MCR p15, 0, ry, c7, c5, 1 ; invalidate icache single entry (MVA)