Digi NS9215 - Manual (Page 456)

I 2 C M A S T E R / S L A V E I N T E R F A C E
Software driver
456 Hardware Reference NS9215
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S o f t w a r e d r i v e r
I
2
C master
software driver
The I 2 C master software driver uses three commands only:
• M_READ to start a read sequence
• M_WRITE to start a write sequence
• M_STOP to give up the I 2 C bus
If, during a read or write sequence, another M_READ or M_WRITE is requested by the
ARM CPU, a restart is performed on the I 2 C bus. This opens the opportunity to
provide a new slave device address in the MAster Address register before the
command request.
I
2
C slave high
level driver
The I
2
C slave high level driver identifies one command: S_STOP , to discontinue a
transaction. After this command, the slave remains inactive until the next start
condition on the I
2 C bus. If a slave is accessed by a master, it generates S_RX_DATA
and S_TX_DATA interrupts (see “Master/slave interrupt codes” on page 455). To
distinguish the transactions from each other, special S_RX_DATA_1ST and
S_TX_DATA_1ST interrupts are generated for the transmitted byte.
0xB S_TX_DATA_1ST Slave TX data required in register TX_DATA , first byte
of transaction
0xC S_RX_DATA_1ST Slave RX data available in register RX_DATA , first
byte of transaction
0XD S_TX_DATA Slave TX data required in register TX_DATA
0xE S_RX_DATA Slave RX data available in register RX_DATA
0XF S_GCA Slave General call address
Code Name Master/slave Description