Digi NS9215 - Manual (Page 147)

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S Y S T E M C O N T R O L M O D U L E
How the quadrature decoder/counter works
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Monitors how far
the encoder has
moved
The counter keeps a running count of how far the encoder has moved.
The decoder increments a 32-bit counter when a state change is found in the
positive direction.
The decoder decrements a 32-bit counter when a state change is found in the
other direction.
When the programmed number reaches the terminal count, the counter is reset and
an interrupt is generated to the CPU. The CPU can also read the counter directly to
sense the direction of the motor.
Typical
application
This diagram shows a typical application of the quadrature decoder/counter:
Digital filter
To ensure the precision and quality of the quadrature decoder/counter, a digital filter
rejects noise on the incoming quadrature signals using three-clock-cycle delayed
filtering. The three-clock-cycle delay filter rejects large and short duration noise
spikes that typically occur in motor system applications.
Testing signals
Each signal is sampled on rising clock edges. A time history of the signals is stored in
a four-bit shift register. Any signal is tested for a stable level that is present for
three consecutive rising clock edges. With this method, pulses shorter than a two-
clock period are rejected.
Timer support
Timer counter 5 supports the sampling clock and the counters.
Motor
Encoder
Quadrature
Decoder/Counter
Controller A
Host