Digi NS9215 - Manual (Page 125)

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W O R K I N G W I T H T H E C P U
External aborts
www.digiembedded.com 125
interpreted in the same way as for a section (see “Interpreting access
permission bits” on page 121).
The only difference is that the fault generated is a page permission fault.
Tiny page: If the level one descriptor defines a page-mapped access and the
level two descriptor is for a tiny page, the AP bits of the level one descriptor
define whether the access is allowed in the same way as for a section. The
fault generated is a page permission fault.
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E x t e r n a l a b o r t s
In addition to MMU-generated aborts, external aborts cam be generated for certain
types of access that involve transfers over the AHB bus. These aborts can be used to
flag errors on external memory accesses. Not all accesses can be aborted in this
way, however.
These accesses can be aborted externally:
Page walks
Noncached reads
Nonbuffered writes
Noncached read-lock-write (SWP) sequence
For a read-lock-write (SWP) sequence, the write is always attempted if the read
externally aborts.
A swap to an NCB region is forced to have precisely the same behavior as a swap to
an NCNB region. This means that the write part of a swap to an NCB region can be
aborted externally.
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E n a b l i n g a n d d i s a b l i n g t h e M M U
Enabling the
MMU
Before enabling the MMU using the R1: Control register, you must perform these
steps:
1
Program the R2: Translation Table Base register and the R3: Domain Access
Control register.
2
Program first-level and second-level page tables as required, ensuring that a
valid translation table is placed in memory at the location specified by the
Translation Table Base register.
When these steps have been performed, you can enable the MMU by setting R1:
Control register bit 0 (the M bit) to high.