Digi NS9215 User Manual
Page 239
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M E M O R Y C O N T R O L L E R
Dynamic Memory Active to Precharge Command Period register
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239
Register bit
assignment
D y n a m i c M e m o r y A c t i v e t o P r e c h a r g e C o m m a n d P e r i o d
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
r e g i s t e r
Address: A070 0034
The Dynamic Memory Active to Precharge Command Period register allows you to
program the active to precharge command period, t
RAS
. It is recommended that this
register be modified during system initialization, or when there are no current or
outstanding transactions. Wait until the memory controller is idle, then enter low-
power or disabled mode. This value normally is found in SDRAM datasheets as t
RAS
.
Note:
The Dynamic Memory Active to Precharge Command Period register is used for
all four dynamic memory chip selects. The worst case value for all chip
selects must be programmed.
Register
Register bit
assignment
Bits
Access
Mnemonic
Description
D31:04
N/A
Reserved
N/A (do not modify)
D03:00
R/W
RP
Precharge command period (t
RP
)
0x0–0xE
n+1 clock cycles, where the delay is in
clk_out
cycles.
0xF
16 clock cycles (reset value on
reset_n
)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
RAS
Bits
Access
Mnemonic
Description
D31:04
N/A
Reserved
N/A (do not modify)
D03:00
R/W
RAS
Active to precharge command period (t
RAS
)
0x0–0xE
n+1 clock cycles, where the delay is in
clk_out
cycles.
0xF
16 clock cycles (reset value on
reset_n
)