Static memory output enable delay 0-3 registers, Static memory output enable delay 0–3 registers, Register bit assignment – Digi NS9215 User Manual
Page 255
. . . . .
M E M O R Y C O N T R O L L E R
Static Memory Output Enable Delay 0–3 registers
www.digiembedded.com
255
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S t a t i c M e m o r y O u t p u t E n a b l e D e l a y 0 – 3 r e g i s t e r s
Address: A070 0208 / 0228 / 0248 / 0268
The Static Memory Output Enable Delay 0–3 registers allow you to program the delay
from the chip select or address change, whichever is later, to the output enable
assertion. The Static Memory Output Enable Delay register is used in conjunction
with the Static Memory Read Delay registers, to control the width of the output
enable signals. It is recommended that these registers be modified during system
initialization, or when there are no current or outstanding transactions. Wait until
the memory controller is idle, then enter low-power or disabled mode.
Register
Register bit
assignment
Bits
Access
Mnemonic
Description
D31:04
N/A
Reserved
N/A (do not modify)
D03:00
R/W
WWEN
Wait write enable (WAITWEN)
0000
One
clk_out
cycle delay between assertion of chip select and
write enable (reset value on
reset_n
).
0001–1111
(n+1)
clk_out
cycle delay, where the delay is
(WAITWEN+1) x t
clk_out
Delay from chip select assertion to write enable.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
WOEN
Bits
Access
Mnemonic
Description
D31:04
N/A
Reserved
N/A (do not modify)
D03:00
R/W
WOEN
Wait output enable (WAITOEN)
0000
No delay (reset value on
reset_n
).
0001–1111n cycle delay, where the delay is
WAITOEN x t
clk_out
Delay from chip select assertion to output enable.