Digi NS9215 - Manual (Page 425)

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S E R I A L C O N T R O L M O D U L E : H D L C
Interrupt Status register
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I n t e r r u p t S t a t u s r e g i s t e r
Address: 9002_9008
The Interrupt Status register provides status about HDLC events. All events are
indicated by reading a 1 and are cleared by writing a 1.
D16 R/W RABORT 0 Enable receive abort error
Enables interrupt generation when a frame is received with
an abort.
D15 N/A Reserved N/A N/A
D14 R/W RXCLS 0 Software receive close
Enables interrupt generation when software forces a buffer
close.
D13:04 N/A Reserved N/A N/A
D03 R/W TBC 0 Enable transmit buffer close
Enables interrupt generation when the HDLC transmit
FIFO indicates to the HDLC transmitter that a byte
corresponds to a buffer close event.
D02 R/W RBC 0 Enable receive buffer close
Enables interrupt generation whenever a buffer close event
is passed from the HDLC receiver to the receive FIFO.
These are the HDLC receive buffer close events:
1
Receive overrun detected
2 Receive abort detected
3 Buffer closed due to invalid CRC
4 Buffer closed due to valid CRC
D01 R/W TX_IDLE 0 Enable transmit idle
Enables interrupt generation whenever the transmitter
moves from the active state to the idle state. This indicates
that the transmit FIFO is empty and the transmitter is not
actively shifting out data.
D00 R/W RX_IDLE 0 Enable receive idle
Enables interrupt generation whenever the receiver moves
from the active state to the idle state. If a start bit is not
received after a stop bit, the receiver enters the idle state.
Bits Access Mnemonic Reset Description