Digi NS9215 - Manual (Page 277)

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E T H E R N E T C O M M U N I C A T I O N M O D U L E
Ethernet Control and Status registers
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E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s
All configuration registers must be accessed as 32-bit words and as single accesses
only. Bursting is not allowed.
Register address
filter
Address Register Description
A060 0000 EGCR1 Ethernet General Control Register #1
A060 0004 EGCR2 Ethernet General Control Register #2
A060 0008 EGSR Ethernet General Status register
A060 000C–A060 0014 Reserved
A060 0018 ETSR Ethernet Transmit Status register
A060 001C ERSR Ethernet Receive Status register
A060 0400 MAC1 MAC Configuration Register #1
A060 0404 MAC2 MAC Configuration Register #2
A060 0408 IPGT Back-to-Back Inter-Packet-Gap register
A060 040C IPGR Non-Back-to-Back Inter-Packet-Gap register
A060 0410 CLRT Collision Window/Retry register
A060 0414 MAXF Maximum Frame register
A060 0418–A060 041C Reserved
A060 0420 MCFG MII Management Configuration register
A060 0424 MCMD MII Management Command register
A060 0428 MADR MII Management Address register
A060 042C MWTD MII Management Write Data register
A060 0430 MRDD MII Management Read Data register
A060 0434 MIND MII Management Indicators register
A060 0440 SA1 Station Address Register #1
A060 0444 SA2 Station Address Register #2
A060 0448 SA3 Station Address register #3
A060 0500 SAFR Station Address Filter register
A060 0504 HT1 Hash Table Register #1
A060 0508 HT2 Hash Table Register #2
A060 0680 STAT Statistics Register Base (45 registers)
A060 0A00 RXAPTR RX_A Buffer Descriptor Pointer register
A060 0A04 RXBPTR RX_B Buffer Descriptor Pointer register
A060 0A08 RXCPTR RX_C Buffer Descriptor Pointer register