Digi NS9215 - Manual (Page 215)

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M E M O R Y C O N T R O L L E R
Asynchronous page mode read: Timing and parameters
www.digiembedded.com 215
External memory
32-bit burst read
from 8-bit
memory
This diagram shows a 32-bit read from an 8-bit page mode ROM device, causing four
burst reads to be performed. A total of eight AHB wait states are added during this
transfer, five AHB arbitration cycles and then one for each of the subsequent reads.
WAITRD and WAITPAGE are 0.
Timing parameter Value
WAITRD 2
WAITOEN 0
WAITPAGE 1
WAITWR N/A
WAITWEN N/A
WAITTURN N/A
A A+4
D(A)
D(A+4) D(A+8)
A+8
clk_out
addr
data
cs[n]
st_oe_n
Timing parameters Value
WAITRD 0
WAITOEN 0
WAITPAGE 0
WAITWR N/A
WAITWEN N/A
WAITTURN N/A
A+3 A A+1 A+2
D(A)
D(A+1) D(A+2) D(A+3)
clk_out
addr
data
cs[n]
st_oe_n