Digi NS9215 - Manual (Page 267)

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E T H E R N E T C O M M U N I C A T I O N M O D U L E
Receive packet processor
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The 2K byte RX_FIFO allows the entire Ethernet frame to be buffered while the
receive byte count is analyzed. The receive byte count is analyzed by the receive
packet processor to select the optimum-sized buffer for transferring the received
frame to system memory. The processor can use one of four different-sized receive
buffers in system memory.
Transmit packet
processor
The transmit packet processor transfers frames constructed in system memory to
the Ethernet MAC. The software initializes a buffer descriptor table in a local RAM
that points the transmit packet processor to the various frame segments in system
memory. The 256-byte TX_FIFO decouples the data transfer to the Ethernet MAC
from the AHB bus fill rate.
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R e c e i v e p a c k e t p r o c e s s o r
As a frame is received from the Ethernet MAC, it is stored in the receive data FIFO.
At the end of the frame, an accept/reject decision is made based on several
conditions. If the packet is rejected, it is flushed from the receive data FIFO.
If a frame is accepted, status signals from the MAC, including the receive size of the
frame, are stored in a separate 32-entry receive status FIFO; the
RX_RD logic is
notified that a good frame is in the FIFO.
If the RX_WR logic tries to write to a full receive data FIFO anytime during the
frame, it flushes the frame from the receive data FIFO and sets RXOVFL_DATA (RX
data FIFO overflowed) in the Ethernet Interrupt Status register. For proper
operation, reset the receive packet processor using the ERX bit in the Ethernet
General Control Register #1 when this condition occurs. If the
RX_WR logic tries to
write a full receive status FIFO at the end of the frame, the RX_WR logic flushes the
frame from the receive data FIFO and sets RXOVFL_STAT (RX status FIFO overflowed)
in the Ethernet Interrupt Status register.
Power down mode
The RX_WR logic supports the processor system power down and recovery
functionality. In this mode, the RX clock to the MAC and the RX_WR logic are still
active, but the clock to the RX_RD and AHB interface is disabled. This allows frames
to be received and written into the receive FIFO, but the frame remains in the FIFO
until the system wakes up. Normal frame filtering is still performed.
When a qualified frame is inserted into the receive FIFO, the receive packet
processor notifies the system power controller, which performs the wake up
sequence. The frame remains in the receive FIFO until the system wakes up.