Digi NS9215 - Manual (Page 496)

T I M I N G
Memory Timing
496 Hardware Reference NS9215
Static RAM
asynchronous
page mode read,
WTPG = 1
WTPG = 1
WTRD = 2
If the PB field is set to 1, all four byte_lane signals will go low for 32-bit,
16-bit, and 8-bit read cycles.
The asynchronous page mode will read 16 bytes in a page cycle. A 32-bit bus
will do four 32-bit reads, as shown (3-2-2-2). A 16-bit bus will do eight 16-bit
reads (3-2-2-2-3-2-2-2) per page cycle, and an 8-bit bus will do sixteen 8-bit
reads (3-2-2-2-3-2-2-2-3-2-2-2-3-2-2-2) per page cycle. 3-2-2-2 is the example
used here, but the WTRD and WTPG fields can set them differently.
Notes:
1 The length of the first cycle in the page is determined by the WTRD field.
2 The length of the 2nd, 3rd, and 4th cycles is determined by the WTPG field.
3 This is the starting address. The least significant two bits will always be ‘00.’
4 The least significant two bits in the second cycle will always be ‘01.’
5 The least significant two bits in the third cycle will always be ‘10.’
6 The least significant two bits in the fourth cycle will always be ‘11.’
7 If the PB field is set to 0, the byte_lane signal will always be high during a read cycle.
8 Setting the BMODE (Burst mode) bit D02 in the static memory configuration register allows the
static output enable signal to toggle during bursts.
N ot e- 1 N o te- 2 N o te- 2 N o te- 2
M 24 M 2 3
M 28 M 2 7
M 20 M 1 9
M 18 M 18 M 1 7
M 26
M 2 5
M 2 6
M 2 5
N ote -3 N ote -4 N ot e- 5 No te- 6
N o te- 7
c l k _ ou t
d ata < 31: 0>
ad dr < 27: 0>
s t_c s _ n< 3: 0>
oe _n
by te _lan e< 3: 0>