Digi NS9215 - Manual (Page 24)

24 Hardware Reference NS9215
ADC Configuration register..................................................................475
ADC Clock Configuration register ..........................................................477
ADC Output Registers 0-7 ...................................................................477
C h a p t e r 1 6 : T i m i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 9
Electrical characteristics ....................................................................479
Absolute maximum ratings ...........................................................479
Recommended operating conditions................................................480
Power dissipation ......................................................................480
DC electrical characteristics................................................................481
Inputs ....................................................................................481
Ouputs ...................................................................................482
Reset and edge sensitive input timing requirements ...................................482
...........................................................................................483
Memory Timing................................................................................484
SDRAM burst read (16-bit)............................................................485
SDRAM burst read (16 bit), CAS latency = 3 .......................................486
SDRAM burst write (16 bit) ...........................................................487
SDRAM burst read (32 bit) ............................................................488
SDRAM burst read (32 bit), CAS latency = 3 .......................................489
SDRAM burst write (32-bit) ...........................................................490
SDRAM load mode......................................................................491
SDRAM refresh mode ..................................................................492
Clock enable timing ...................................................................493
Values in SRAM timing diagrams.....................................................494
Static RAM read cycles with 0 wait states .........................................495
Static RAM asynchronous page mode read, WTPG = 1 ...........................496
Static RAM read cycle with configurable wait states ............................497
Static RAM sequential write cycles .................................................498
Static RAM write cycle ................................................................499
Static write cycle with configurable wait states .................................500
Slow peripheral acknowledge timing ...............................................501
Slow peripheral acknowledge read .................................................502
Slow peripheral acknowledge write ................................................502
Ethernet timing ........................................................................503
Ethernet MII timing ....................................................................503
I
2
C timing ...............................................................................504
SPI Timing...............................................................................505
SPI master mode 0 and 1: 2-byte transfer .........................................507
SPI master mode2 and 3: 2-byte transfer ..........................................507
SPI slave mode 0 and 1: 2-byte transfer ...........................................508
SPI slave mode 2 and 3: 2-byte transfer ...........................................508
Reset and hardware strapping timing .....................................................509
JTAG timing ...................................................................................510