Hdlc clock divider high – Digi NS9215 User Manual
Page 431
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S E R I A L C O N T R O L M O D U L E : H D L C
HDLC Clock Divider High
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431
Use the HDLC CLock Divider Low register to set bits 07:00 of the clock divider. This
is the equation for the HDLC clock rate:
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H D L C C l o c k D i v i d e r H i g h
Address: 9002_911C
Use the HDLC CLock Divider High register to set bits 14:08 of the clock divider.
Register
HDLC rate (bps) =
29.4912 MHz
16 x (DIV = 1)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Not used
Not used
DIVL
Bits
Access
Mnemonic
Reset
Description
D31:08
R
Not used
0
Write this field to 0.
D07:00
R/W
DIVL
0
Eight LSBs of the divider that generates the HDLC
transmit and receive clock.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Not used
Not used
DIVH
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