Digi NS9215 - Manual (Page 306)

E T H E R N E T C O M M U N I C A T I O N M O D U L E
Statistics registers
306 Hardware Reference NS9215
Receive alignment
error counter
(A060 06BC)
Incremented for each received frame, from 64 to 1518 bytes, that contains an
invalid FCS and has dribble bits (that is, is not an integral number of bytes).
Receive code
error counter
(A060 06C4)
Incremented each time a valid carrier was present and at least one invalid data
symbol was found.
Receive carrier
sense error
counter (A060
06C8)
Incremented each time a false carrier is found during idle, as defined by a 1 on
RX_ER and an 0xE on RXD. The event is reported with the statistics generated on the
next received frame. Only one false carrier condition can be detected and logged
between frames.
Receive undersize
packet counter
(A060 06CC)
Incremented each time a frame is received that is less than 64 bytes in length,
contains a valid FCS, and is otherwise well-formed. This counter does not look at
range/length errors.
Receive oversize
packet counter
(A060 06D0)
Incremented each time a frame is received that exceeds 1518 bytes (non-VLAN) or
1522 bytes (VLAN), contains a valid FCS, and is otherwise well-formed. This counter
does not look at range/length errors. This counter is not incremented when a
packet is truncated because it exceeds the MAXF value.
Receive fragments
counter (A060
06D4)
Incremented for each frame received that is less than 64 bytes in length and
contains an invalid FCS; this includes integral and non-integral lengths.
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 RALN
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 RCDE
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 RCSE
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 RUND
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 ROVR
D31:12 R Reserved
D11:00 R/W Reset = 0x000 RFRG