Digi NS9215 - Manual (Page 418)

S E R I A L C O N T R O L M O D U L E : H D L C
Digital phase-locked-loop (DPLL) operation: Encoding
418 Hardware Reference NS9215
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D i g i t a l p h a s e - l o c k e d - l o o p ( D P L L ) o p e r a t i o n : E n c o d i n g
In the HDLC module, the internal clock comes from the output of the dedicated
divider. The divider output is divided by 16 to form the transmit clock and is fed to
the DPLL to form the receive clock. The DPLL basically is a divide-by-16 counter
that uses the transition timings on the receive data stream to adjust its count. The
DPLL adjusts the count so the DPLL output is placed properly in the bit cells to
sample the receive data.
Transitions
To work properly, the receive data stream requires transitions. NRZ data encoding
does not guarantee transitions in all cases (for example, a long string of zeroes), but
the other data encodings do. NRZI guarantees transitions because of inserted zeroes.
The Biphase encodings all have at least one transition per bit cell.
NRZ Data
HDLC Clock
NRZI
NRZI
Biphase-Level
Biphase-Space
Biphase-Space
Biphase-Mark
Biphase-Mark
data 1 0 1 0 0 1 1 0