Digi NS9215 - Manual (Page 208)

M E M O R Y C O N T R O L L E R
Static memory controller
208 Hardware Reference NS9215
Notes:
Buffering enables the transaction order to be rearranged to improve memory
performance. If the transaction order is important, the buffers must be
disabled.
Extended wait and page mode cannot be enabled at the same time.
Write protection
Each static memory chip select can be configured for write-protection. SRAM
usually is unprotected and ROM devices must be write-protected (to avoid potential
bus conflict when performing a write access to ROM), but the P field in the Static
Memory Configuration register (see “StaticMemory Configuration 0–3 registers” on
page 251) can be set to write-protect SRAM as well as ROM devices. If a write access
is made to a write-protected memory bank, a bus error occurs. If a write access is
made to a memory bank containing ROM devices and the chip select is not write-
protected. An error is not returned and the write access proceeds as normal. Note
that this might lead to a bus conflict.
Extended wait
transfers
The static memory controller supports extremely long transfer times. In normal use,
the memory transfers are timed using the Static Memory Read Delay register
(StaticWaitRd) and Static Memory Wait Delay register (StaticWaitWr). These
registers allow transfers with up to 32 wait states. If a very slow static memory
device has to be accessed, however, you can enable the static configuration
extended wait (EW) bit. When EW is enabled, the Static Extended Wait register is
used to time both the read and write transfers. The Static Extended Wait register
allows transfers to have up to 16368 wait states.
A peripheral can, at any time, signal to the processor that it wants to complete an
access early by asserting the
ns_ta_strb signal. This allows a slow peripheral with
variable access times to signal that it is ready to complete an access. The processor
normally completes an access when it finds a rising edge on
ns_ta_strb .
For a burst access, the peripheral must toggle ns_ta_strb for each access it wants to
complete early. The peripheral is not required to assert ns_ta_strb for each access in
the burst; for example, the peripheral requires the programmed access for the start
of a four access burst followed by three early completion accesses, each signalled
by the assertion of
ns_ta_strb .
Using the ns_ta_strb signal is valid only when the EW bit is enabled.
Be aware:
Using extremely long transfer times might mean that SDRAM devices are not
refreshed correctly.
Very slow transfers can degrade system performance, as the external memory
interface is tied up for long periods of time. This has detrimental effects on