Table walk process first-level fetch – Digi NS9215 User Manual

Page 109

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MemoryManagement Unit (MMU)

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109

Table walk
process

First-level fetch

Bits [31:14] of the TTB register are concatenated with bits [31:20] of the MVA to
produce a 30-bit address.

Indexed by
modified
virtual
address
bits [31:20]

TTB base

Translation

table

Section base

Indexed by
modified
virtual
address
bits [19:0]

4096 entries

1 MB

Section

Large page

Indexed by
modified
virtual
address
bits [15:0]

Large page
base

Coarse page

table

Coarse page

table base

Fine page

table base

Fine page

table

Indexed by
modified
virtual
address
bits [19:10]

256 entries

Indexed by
modified
virtual
address
bits [19:12]

1024 entries

Indexed by
modified
virtual
address
bits [11:0]

Indexed by
modified
virtual
address
bits [9:0]

64 KB

4 KB

1 KB

Tiny page

Small page

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