Digi NS9215 - Manual (Page 87)

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W O R K I N G W I T H T H E C P U
R0: ID code and cache type status registers
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You can access the cache type register by reading CP15 register R0 with the opcode_2
field set to 1. Note this example:
MRC p15, 0, Rd, c0, c0, 1; returns cache details
Cache type
register and field
description
Dsize and Isize
fields
The Dsize and Isize fields in the cache type register have the same format, as
shown:
The field contains these bits:
Field Description
Ctype Determines the cache type, and specifies whether the cache supports lockdown and how it is
cleaned. Ctype encoding is shown below; all unused values are reserved.
Value: 0b1110
Method: Writeback
Cache cleaning: Register 7 operations (see “R7:Cache Operations register” on page 94)
Cache lockdown: Format C (see “R9: Cache Lockdown register” on page 98)
S bit Specifies whether the cache is a unified cache (S=0) or separate ICache and DCache (S=1).
Will always report separate ICache and DCache for this processor.
Dsize Specifies the size, line length, and associativity of the DCache.
Isize Species the size, length and associativity of the ICache.
Ctype 0 S Dsize
31 28 25 24 23 12
0 0 Isize
11 10 9 6 5 3 2 1 0
0 0 Size M Assoc Len