Dynamic memory self-refresh exit time register – Digi NS9215 User Manual

Page 240

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M E M O R Y C O N T R O L L E R

Dynamic Memory Self-refresh Exit Time register

240

Hardware Reference NS9215

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D y n a m i c M e m o r y S e l f - r e f r e s h E x i t T i m e r e g i s t e r

Address: A070 0038

The Dynamic Memory Self-refresh Exit Time register allows you to program the self-
refresh exit time, t

SREX

. It is recommended that this register be modified during

system initialization, or when there are no current or outstanding transactions. Wait
until the memory controller is idle, then enter low-power or disabled mode. This
value normally is found in SDRAM data sheets as t

SREX

.

Note:

The Dynamic Memory Self-refresh Exit Time register is used for all four
dynamic memory chip selects. The worst case value for all chip selects must
be programmed.

Register

Register bit
assignment

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D y n a m i c M e m o r y L a s t D a t a O u t t o A c t i v e T i m e r e g i s t e r

Address: A070 003C

The Dynamic Memory Last Data Out to Active Time register allows you to program
the last-data-out to active command time, t

APR

. It is recommended that this

register be modified during system initialization, or when there are no current or
outstanding transactions. Wait until the memory controller is idle, then enter low-
power or disabled mode. This value normally is found in SDRAM datasheets as t

APR

.

Note:

The Dynamic Memory Last Data Out to Active Time register is used for all four
dynamic memory chip selects. The worst case value for all chip selects must
be programmed.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

31

29

28

27

26

25

24

23

22

21

20

19

18

17

16

30

Reserved

Reserved

SREX

Bits

Access

Mnemonic

Description

D31:04

N/A

Reserved

N/A (do not modify)

D03:00

R/W

SREX

Self-refresh exit time (t

SREX

)

0x0–0xE

n+1 clock cycles, where the delay is in

clk_out

cycles.

0xF

16 clock cycles (reset value on

reset_n

)

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