Digi NS9215 - Manual (Page 292)

E T H E R N E T C O M M U N I C A T I O N M O D U L E
Non Back-to-Back Inter-Packet-Gap register
292 Hardware Reference NS9215
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N o n B a c k - t o - B a c k I n t e r - P a c k e t - G a p r e g i s t e r
Address: A060 040C
Register
Bits Access Mnemonic Reset Description
D31:07 N/A Reserved N/A N/A
D06:00 R/W IPGT 0x00 Back-to-back inter-packet-gap
Programmable field that indicates the nibble time offset
of the minimum period between the end of any
transmitted frame to the beginning of the next frame.
Full-duplex mode
Register value should be the appropriate period in
nibble times minus 3.
Recommended setting is 0x15 (21d) , which
represents the minimum IPG of 0.96 uS (in 100
Mbps) or 9.6uS (in 10 Mbps).
Half-duplex mode
Register value should be the appropriate period in
nibble times minus 6.
Recommended setting is 0x12 (18d) , which
represents the minimum IPG of 0.96 uS (in 100
Mbps) or 9.6 uS (in 10 Mbps).
Reserved
IPGR2
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
IPGR1 Rsvd Rsvd