General arbiter control register, Brc0, brc1, brc2, and brc3 registers – Digi NS9215 User Manual
Page 158
S Y S T E M C O N T R O L M O D U L E
General Arbiter Control register
158
Hardware Reference NS9215
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G e n e r a l A r b i t e r C o n t r o l r e g i s t e r
Address: A090 0000
The General Arbiter Control register controls whether the CPU access is routed
through the main arbiter or is connected directly to the memory controller.
Register
Register bit
assignment
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B R C 0 , B R C 1 , B R C 2 , a n d B R C 3 r e g i s t e r s
Addresses: A090 0004 / 0008 / 000C / 0010
The BRC[0:3] registers control the AHB arbiter bandwidth allocation scheme.
A090 0214
External Interrupt 0 Control register
A090 0218
External Interrupt 1 Control register
A090 021C
External Interrupt 2 Control register
A090 0220
External Interrupt 3 Control register
A090 0224
RTC Module Control
A090 0228
Power Management
A090 022C
AHB Bus Activity Status
Offset
[31:24]
[23:16]
[15:8]
[7:0]
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
Arb
Control
Bits
Access
Mnemonic
Reset
Description
D31:01
N/A
Reserved
N/A
N/A
D00
R
ArbControl
0x0
Arbiter control
0
CPU connected directly to memory controller
1
CPU connected to main arbiter