Digi NS9215 - Manual (Page 204)

M E M O R Y C O N T R O L L E R
Low-power operation
204 Hardware Reference NS9215
Power-saving modes that dynamically control SDRAM clk_en .
Dynamic memory self-refresh mode supported by a power management unit
(PMU) interface or by software.
Controller supports 2K, 4K, and 8K row address synchronous memory parts;
that is, typical 512 MB, 256 MB, and 16 Mb parts with 8, 16, or 32 DQ bits per
device.
A separate AHB interface to program the memory controller. This enables the
memory controller registers to be situated in memory with other system
peripheral registers.
Locked AHB transaction support.
Support for all AHB burst types.
Little and big endian support.
Note:
Synchronous static memory devices (synchronous burst mode) are not
supported.
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L o w - p o w e r o p e r a t i o n
In many systems, the contents of the memory system have to be maintained during
low-power sleep modes. The processor provides two features to enable this:
Dynamic memory refresh over soft reset
A mechanism to place the dynamic memories into self-refresh mode
Self-refresh mode can be entered as follows:
1
Set the SREFREQ bit in the Dynamic Memory Control register.
2
Poll the SREFACK bit in the Status register.
Note:
Static memory can be accessed as normal when the SDRAM memory is in self-
refresh mode.
Low-power
SDRAM deep-
sleep mode
The memory controller supports JEDEC low-power SDRAM deep-sleep mode. Deep-
sleep mode can be entered by setting the deep-sleep (DP) bit in the Dynamic
Memory Control register. The device is put into a low-power mode where it is
powered down and no longer refreshed. All data in the memory is lost.
Low-power
SDRAM partial
array refresh
The memory controller supports JEDEC low-power SDRAM partial array refresh.
Partial array refresh can be programmed by initializing the SDRAM memory device
appropriately. When the memory device is put into self-refresh mode, only the
memory banks specified are refreshed. The memory banks that are not refreshed
lose their data contents.