Digi NS9215 - Manual (Page 276)

E T H E R N E T C O M M U N I C A T I O N M O D U L E
Clock synchronization
276 Hardware Reference NS9215
Multicast address
filtering example
2
To accept multicast packets with destination addresses in the range of
0x01_00_5E_00_00_00 to 0x01_00_5E_00_00_0f using entry 4, the registers are set as
shown:
Notes
If any of the address filter entries are enabled, the SAL must be set up to
accept all multicast packets by setting the PRM bit in the Station Address Filter
register.
Runt packets that are less than 6 bytes, and therefore do not have a valid
destination address, are automatically discarded by the multicast address
filtering logic.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C l o c k s y n c h r o n i z a t i o n
The multicast filtering logic resides in the RX CLK domain, but all of the registers
are controlled in the AHB clock domain. To provide traditional dual-rank clock
synchronization flops for each bit of the five Multicast Address Filter registers
consumes a large amount of gates. Therefore, the logic is designed such that only
the MFILTEN register bits are synchronized and when these bits are cleared, changes
in the other register values are not seen at the input of any internal flops in the RX
CLK domain.
Writing to other
registers
Use these steps to dynamically write to any of the other Multicast Address Filter
registers:
1
Clear the enable bit in the MFILTEN register for the address filter you want to
change.
2
Update the address filter registers for the disable filter.
3
Set the enable bit for the address filter that was just changed.
If the address filters are changed only when the RX_WR logic is reset or not
processing frames, as recommended, the address filter registers can be updated
without using this procedure.
Register Value Function
MFILTEN 0x10 Enable entry 4
MFILTL4 0x5E_00_00_00 Lower 32 bits of multicast address
MFILTH4 0x01_00 Upper 16 bits of multicast address
MCMSKL4 0xFFFF_FFF0 Include only bits [31:04] of the lower 32 bits of the
multicast address in the comparison.
MCMSKH4 0xFFFF Include all of the upper 16 bits of the multicast address
in the comparison