Digi NS9215 - Manual (Page 375)

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I / O H U B M O D U L E
[Module] DMA RX Control
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[ M o d u l e ] D M A R X C o n t r o l
Addresses: 9000_0004 / 9000_8004 / 9001_0004 / 9001_8004 / 9002_0004 /
9002_8004 / 9003_0004 / 9003_8004
The DMA RX Control register contains control register settings for each receive DMA
channel.
D18 R MODIP 0x0 Module interrupt pending
The hardware module has asserted an interrupt.
Software must read the appropriate Interrupt
Status register to determine the cause.
D17:16 N/A Reserved N/A N/A
D15 R RXPBUSY 0x0 0 Peripheral idle
1 Peripheral busy
Note: Applicable only for channels connected
to the flexible I/O module processors.
The CPU must not access the Module Direct
Mode RX Data FIFO Read register when this bit
is set. If this bit is set, the read generates a bus
error.
D14 R RX FIFO full 0x0 Receive status and data FIFO full status
0
Not full
1 Full
D13 R RX FIFO empty 0x1 Receive status and data FIFO empty status
0
Not empty
1 Empty
D12 R TXPBUSY 0x0 0 Peripheral idle
1 Peripheral busy
Note: Applicable only for channels connected
to the flexible I/O module processors.
The CPU must not access the Module Direct
Mode TX Data FIFO register when this bit is set.
If this bit is set, the read generates a bus error.
D11 R TX FIFO full 0x0 Transmit data FIFO full status
0
Not full
1 Full
D10 R TX FIFO empty 0x1 Transmit data FIFO empty status
0
Not empty
1 Empty
D09:00 N/A Reserved N/A N/A
Bit(s) Access Mnemonic Reset Description