Altera PCI Compiler - Manual (Page 10)

x User Guide Version 11.1 Altera Corporation
PCI Compiler
Contents
Ordering PCI-to-Avalon Operations ...................................................................................... 7–42
PCI Host-Bridge Operation ................................................................................................................ 7–45
Altera-Provided PCI Bus Arbiter ...................................................................................................... 7–45
Interrupts .............................................................................................................................................. 7–46
Generation of PCI Interrupts ................................................................................................... 7–46
Reception of PCI Interrupts ..................................................................................................... 7–46
Generation of Avalon-MM Interrupts ................................................................................... 7–47
Control & Status Registers ................................................................................................................. 7–47
PCI Interrupt Status Register ........................................................................................................ 7–49
PCI Interrupt Enable Register ...................................................................................................... 7–51
PCI Mailbox Register Access ........................................................................................................ 7–52
Avalon-to-PCI Address Translation Table ................................................................................. 7–53
Read-Only Configuration Registers ............................................................................................ 7–54
Avalon-MM Interrupt Status Register ........................................................................................ 7–56
Avalon-MM Interrupt Enable Register ....................................................................................... 7–60
Avalon Mailbox Register Access .................................................................................................. 7–60
Chapter 8. Testbench
General Description ............................................................................................................................... 8–1
Features ................................................................................................................................................... 8–2
PCI Testbench Files ............................................................................................................................... 8–3
Testbench Specifications ....................................................................................................................... 8–4
Master Transactor (mstr_tranx) ...................................................................................................... 8–5
PROCEDURES and TASKS Sections ........................................................................................ 8–5
INITIALIZATION Section ......................................................................................................... 8–6
USER COMMANDS Section ..................................................................................................... 8–7
cfg_rd ............................................................................................................................................ 8–7
cfg_wr ........................................................................................................................................... 8–8
mem_wr_32 .................................................................................................................................. 8–8
mem_rd_32 .................................................................................................................................. 8–9
mem_wr_64 ................................................................................................................................ 8–10
mem_rd_64 ................................................................................................................................ 8–11
io_wr ........................................................................................................................................... 8–11
io_rd ............................................................................................................................................ 8–11
Target Transactor (trgt_tranx) ...................................................................................................... 8–12
FILE IO section .......................................................................................................................... 8–13
PROCEDURES and TASKS sections ...................................................................................... 8–13
Bus Monitor (monitor) ................................................................................................................... 8–13
Arbiter (arbiter) .............................................................................................................................. 8–14
Pull Up (pull_up) ........................................................................................................................... 8–14
Simulation Flow ................................................................................................................................... 8–15
Appendix A. Using PCI Constraint File Tcl Scripts
Introduction ........................................................................................................................................... A–1
PCI Constraint Files .............................................................................................................................. A–1
Simultaneous Switching Noise (SSN) Considerations .................................................................... A–2
Additional Options ............................................................................................................................... A–3