Pci_mt64 megacore function reference design – Altera PCI Compiler User Manual

Page 55

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Altera Corporation

User Guide Version 11.1

1–21

October 2011

PCI Compiler

Getting Started

<path>/pci_compiler/megawizard_flow
/ref_designs/pci_mt32/vhdl/sdr_intf

<path>/pci_compiler/megawizard_flow
/ref_designs/pci_mt32/vhdl/sdr_cntrl

f

Refer to Quartus II help for information on how to add
user libraries in the Quartus II software.

3.

Include the following files in your Quartus II project:

<path>/pci_compiler/megawizard_flow
/ref_designs/pci_mt32/vhdl/chip_top

/vhdl_components.vhd

<path>/pci_compiler/megawizard_flow
/ref_designs/pci_mt32/vhdl/pci_top/pci_top.vhd

4.

Select the appropriate Altera device for your project.

Use an Altera-provided PCI constraint file.

f

For more information on using PCI constraint files, refer to

Appendix A, Using PCI Constraint File Tcl Scripts

.

5.

Compile your project.

pci_mt64 MegaCore Function Reference Design

The pci_mt64 MegaCore Function Reference Design is an example that
shows how to connect the local-side signals of the Altera pci_mt64
MegaCore function to local-side applications when the MegaCore
function is used as a master or target on the PCI bus. The reference design
consists of the following elements:

Master control logic

Target control logic

DMA engine

Data path FIFO buffer functions

SDRAM interface

The pci_mt64 MegaCore Function Reference Design requires the Quartus
II software.

Table 1–7

describes the directory structure of the pci_mt64 MegaCore

Function Reference Design. The directory names are relative to the
following path:

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