Altera PCI Compiler - Manual (Page 315)

Altera Corporation User Guide Version 11.1 7–47
October 2011
Functional Description
The Avalon-MM interrupt status register contains two bits that indicate
whether a rising- or falling-edge is detected on intan. Similarly, the
Avalon-MM interrupt enable register has two bits that enable the
signaling of an Avalon-MM interrupt on either a rising- or falling-edge of
the Avalon-MM interrupt enable register. For a complete description of
the Avalon-MM interrupt status register and Avalon-MM interrupt
enable register, refer to
Table 7–26 on page 7–57 and Table 7–28 on
page 7–60 .
MSI interrupts can be received by using the PCI-to-Avalon mailbox
registers - read/write as the target of the PCI MSI messages. MSI
interrupts can also be received by another Avalon-MM slave specifically
designed to process them.
Generation of Avalon-MM Interrupts
Avalon-MM interrupts (the CraIrq_o signal) can be generated by a
variety of error conditions, mailbox writes, or PCI interrupt signals. For a
complete list of Avalon-MM interrupts, refer to the Avalon-MM interrupt
status register (
Table 7–26 on page 7–57 ) and the Avalon-MM interrupt
enable register ( Table 7–28 on page 7–60 ).
Control & Status
Registers These registers are accessible from the Control Register Access
Avalon Slave
port. If you do not enable the Control Register
Access Avalon Slave port (refer to “Avalon Configuration” on
page 6–16 ), none of the control and status registers will be implemented.
The control and status register space is spread over a 16-KByte region,
with each 4-KByte sub-region containing a specific set of functions that
may be specific to accesses from either:
■ PCI processors only
■ Avalon processors only
■ From both types of processors