Altera PCI Compiler - Manual (Page 125)

Altera Corporation User Guide Version 11.1 3–51
October 2011
Functional Description
Table 3–35 shows the sequence of events for a 64-bit single-cycle memory
read target transaction. The 64-bit extension signals are not applicable to
the pci_mt32 and pci_t32 MegaCore functions.
Table 3–35. Single-Cycle Memory Read Target Transaction (Part 1 of 2)
Clock Cycle Event
1 The PCI bus is idle.
2 The address phase occurs.
3 The PCI MegaCore function latches the address and command, and decodes the address to
check if it falls within the range of one of its BARs. During clock cycle 3, the master deasserts
the
framen and req64n signals and asserts irdyn to indicate that only one data phase
remains in the transaction. For a single-cycle memory read, this phase is the only data phase
in the transaction. The PCI MegaCore function begins to decode the address during clock
cycle 3, and if the address falls in the range of one of its BARs, the transaction is claimed.
The PCI master tri-states the ad bus for the turn-around cycle.
4 If the PCI MegaCore function detects an address hit in clock cycle 3, several events occur
during clock cycle 4:
● The PCI MegaCore function informs the local-side device that it is claiming the read
transaction by asserting
lt_framen and the bit on lt_tsr[5..0] that corresponds to
the BAR range hit. In Figure 3–7 , lt_tsr[0] is asserted indicating that a base address
register zero hit.
● The MegaCore function drives the transaction command on l_cmdo[3..0] and
address on l_adro[31..0] .
● The PCI MegaCore function turns on the drivers of devseln , ack64n , trdyn , and
stopn , getting ready to assert devseln and ack64n in clock cycle 5.
● lt_tsr[7] is asserted to indicate that the pending transaction is 64-bits.
● lt_tsr[8] is asserted to indicate that the PCI side of the PCI MegaCore function is
busy.
5 The PCI MegaCore function asserts devseln and ack64n to claim the transaction. The
function also drives lt_ackn to the local-side device to indicate that it is ready to accept data
on the l_adi bus. The PCI MegaCore function also enables the output drivers of the ad bus
to ensure that it is not tri-stated for a long time while waiting for valid data. Although the local
side asserts
lt_rdyn during clock cycle 5, the data transfer does not occur until clock
cycle 6.
6 lt_rdyn is asserted in clock cycle 5, indicating that valid data is available on the l_adi bus
in clock cycle 6. The PCI MegaCore function registers the data into its internal pipeline on the
rising edge of clock cycle 7. The local side transfer is indicated by the
lt_dxfrn signal. The
lt_dxfrn signal is low during the clock cycle where a data transfer on the local side occurs.
The local side data transfer occurs if lt_ackn is asserted on the current clock edge while
lt_rdyn is asserted on the previous clock edge. The lt_dxfrn signal is asserted to
indicate a successful data transfer.
7 The rising edge of clock cycle 7 registers the valid data from the l_adi bus and drives the
data on the ad bus. At the same time, the PCI MegaCore function asserts the trdyn signal
to indicate that there is valid data on the ad bus.