Altera PCI Compiler - Manual (Page 276)

7–8 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Functional Overview
Figure 7–3. PCI-Avalon Bridge Managing the PCI Target-Only Peripheral Mode, Burst Transfers
You can customize the Target-Only mode by specifying one of the
performance profiles. Refer to
“Performance Profiles” on page 7–11 .
PCI Master/Target Peripheral Mode Operation
Figure 7–4 shows the block diagram of the PCI-Avalon bridge managing
the connectivity of the PCI Master/Target Peripheral mode. The PCI
Master/Target Peripheral mode uses at least one Avalon-MM master
port, the PCI Bus Access Slave port, and has a Host processor and bus
arbiter on the PCI bus side.
Figure 7–4 shows an example when both
Avalon-MM master ports are used.
PCI- A v alon B r idg e
T arget-Only P e r iphe r al Mode
With Either Burst T r ans f ers with Single P ending Read ,
or Burst T r ans f ers with Multiple P ending Read s
PCI
T arge t
Controller
Master
P
o
r t
PCI
MegaCore
Function
Non-
Pre f etcha b l e
A v alo n
Master
Host
Processor
PCI
Master/
T arge t
D e vic e
PCI
Bus
Arbiter
Pre f etcha b le
A v alo n
Master
PCI
Pre f etcha b l e
B r idg e
Logic
PCI
Non-
Pre f etcha b l e
B r idge Logi c
PCI Clo c k A v alon Clo c k
PCI
Bus
Avalon
Slave
Peripheral
Avalon
Slave
Peripheral
System
Interconnect
Fabric