Altera PCI Compiler - Manual (Page 116)

3–42 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Configuration Registers
The PCI MegaCore functions allow you to set a default expansion ROM
base address using the hardwire option in the Parameterize - PCI
Compiler
wizard. Using a hardwire BAR allows the function to claim
transactions without requiring the configuration of the expansion ROM
BAR. When using the hardwire expansion ROM BAR feature, the
expansion ROM BAR attributes must indicate the appropriate BAR
settings.
1 When implementing a hardwire expansion ROM BAR, the
corresponding BARs become read only. However, bit 0 is
read/write, allowing you to disable the expansion ROM BAR
after power-up.
Capabilities Pointer
The capabilities pointer register is an 8-bit read-only register that can be
enabled through the wizard. The capabilities pointer value entered
through the wizard points to the first item in the list of capabilities. For a
list of the capability IDs, refer to Appendix H of the PCI Local Bus
Specification, Revision 3.0. The address value of this pointer must be 0x40
or greater, and each capability must be within DWORD boundaries. Refer
to
Table 3–29 .
Configuration transactions to addresses greater than or equal to 0x40 are
transferred to the local side of the PCI MegaCore functions and operate as
32-bit transactions. The local side must implement the necessary logic for
the capabilities registers.
Interrupt Line Register
The interrupt line register is an 8-bit register that defines to which system
interrupt request line (on the system interrupt controller) the intan
output is routed. The interrupt line register is written by the system
software upon power-up; the default value is 0x00.
Table 3–30 shows the
Table 3–29. Capabilities Pointer Format
Data Bit Mnemonic Read/Write Definition
7..0 cap_ptr Read/write Capabilities pointer
register