Burst transfers with single pending read, Burst transfers with multiple pending reads, Interface signals – Altera PCI Compiler User Manual
Page 281: Interface signals –13
Altera Corporation
User Guide Version 11.1
7–13
October 2011
Functional Description
Burst Transfers With Single Pending Read
This profile provides high throughput for transactions initiated by
Avalon-MM master devices to PCI target devices via the PCI bus master
interface. This profile uses embedded RAM blocks to enable clock
domain crossing and efficient processing of single-cycle and burst
transfers. Avalon-MM read transactions are implemented as latent read
transfers. The PCI master devices issue only one read transaction at a
time.
Burst Transfers With Multiple Pending Reads
This profile is exactly the same as the Burst Transfers with Single Pending
Read for both the PCI Master/Target Peripheral and PCI Host-Bridge
Device operational modes except that it can simultaneously process up to
four pending reads. This allows higher throughput for read operations,
but also requires more device resources.
For more information on multiple pending read transactions, refer to
“Value of Multiple Pending Reads” on page 6–6
Interface
Signals
The PCI-Avalon bridge has PCI and Avalon-MM interface signals. The
SOPC Builder automatically connects the Avalon-MM interface signals.
f
For information about Avalon-MM interface signals and their
functionality, refer to the
chapter in volume 4 of the Quartus II Handbook.
The SOPC Builder appends the instance name of the PCI Compiler
component to all of the corresponding PCI-Avalon bridge component’s
signal names. For example, if the instance name of the PCI Compiler
component is pci_compiler, all of PCI-Avalon bridge component’s
signal names will be <signal name>_pci_compiler, where <signal
name> is the default signal name.
The SOPC Builder system containing the PCI-Avalon bridge has one
asynchronous reset signal named rstn_<pci_compiler_instance_name>.
This signal is used for the entire SOPC Builder system, including the
PCI-Avalon bridge. A second reset signal, reset_n, can be enabled by
selecting Independent Avalon Reset Signal when setting up the
PCI-Avalon bridge. This signal is used for the entire SOPC Builder system
except the PCI-Avalon bridge.
The connection of the reset signal, rstn_<pci_compiler_instance_name>, is
generally a system-specific requirement and is outside the scope of this
document. However, for most PCI applications, this reset signal should
be connected to the PCI reset signal and must meet all PCI reset