Altera PCI Compiler - Manual (Page 16)

4 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Features
■ IP functional simulation models enable simulation of a register
transfer level (RTL) model of a PCI MegaCore function in VHDL and
Verilog HDL simulators
■ OpenCore Plus hardware evaluation feature enables testing of a
PCI MegaCore function in hardware prior to purchasing a license
■ Configuration registers:
● Parameterized registers: device ID, vendor ID, class code,
revision ID, BAR0 through BAR5, subsystem ID, subsystem-
vendor ID, maximum latency, minimum grant, capabilities list
pointer, expansion ROM BAR
● Parameterized default or preset base address (available for all
six BARs) and expansion ROM base address
● Non-parameterized registers: command, status, header type 0,
latency timer, cache line size, interrupt pin, interrupt line
■ Host bridge application support
PCI Compiler with MegaWizard Plug-in Manager Flow
The following list outlines the features of the PCI Compiler with
MegaWizard Plug-in Manager flow.
■ IP Toolbench wizard-driven interface makes it easy to generate a
custom variation of a PCI MegaCore function
■ PCI target features:
● Capabilities list pointer support
● Expansion ROM BAR support
● Local-side requests for target abort, retry, or disconnect
● Local-side interrupt requests
■ PCI master features (pci_mt64 and pci_mt32 only):
● Allows on-chip arbitration logic
● Allows disabling latency timer
■ 64-bit PCI features (pci_mt64 and pci_t64 only):
● 64-bit addressing support as both master and target
● Initiates 64-bit addressing, using dual-address cycle (DAC)
● Initiates 64-bit memory transactions
● Dynamically negotiates 64-bit transactions and automatically
multiplexes data on the local 64-bit data bus
PCI Compiler with SOPC Builder Flow
The following list outlines the features of the PCI Compiler with SOPC
Builder flow.
■ SOPC Builder ready
■ PCI complexities, such as retry and disconnect are handled by the
PCI/Avalon Bridge logic and transparent to the user