Altera PCI Compiler - Manual (Page 205)

Altera Corporation User Guide Version 11.1 3–131
October 2011
Functional Description
64-Bit
Addressing,
Dual Address
Cycle (DAC) This section describes and includes waveform diagrams for 64-bit
addressing transactions using a dual address cycle (DAC). All 32-bit
addressing transactions for master and target mode operation described
in the previous sections are supported by 64-bit addressing transactions.
This includes both 32-bit and 64-bit data transfers.
1 This section applies to the pci_mt64 and pci_t64 MegaCore
functions only.
Target Mode Operation
A read or write transaction begins after a master acquires mastership of
the PCI bus and asserts framen to indicate the beginning of a bus
transaction. If the transaction is a 64-bit transaction, the master device
asserts the req64n signal at the same time it asserts the framen signal.
The pci_mt64 and pci_t64 functions assert the framen signal in the
first clock cycle, which is called the first address phase. During the first
address phase, the master device drives the 64-bit transaction address on
ad[63..0]
, the DAC command on cben[3..0], and the transaction
command on cben[7..4]. On the following clock cycle, during the
second address phase, the master device drives the upper 32-bit
transaction address on both ad[63..32] and ad[31..0], and the
transaction command on both cben[7..4] and cben[3..0]. During
these two address phases, the PCI MegaCore function latches the
transaction address and command, and decodes the address. If the
transaction address matches the pci_mt64 and pci_t64 target, the
pci_mt64
and pci_t64 target asserts the devseln signal to claim the
transaction. In 64-bit transactions, pci_mt64 and pci_t64 also assert
the ack64n signal at the same time as the devseln signal indicating that
pci_mt64
and pci_t64 accept the 64-bit transaction. The pci_mt64
and pci_t64 functions implement slow decode, i.e., the devseln and
ack64n
signals are asserted after the second address phase is presented
on the PCI bus. Also, both of the lt_tsr[1..0] signals are driven high
to indicate that the BAR0 and BAR1 address range matches the current
transaction address.