Altera PCI Compiler - Manual (Page 291)

Altera Corporation User Guide Version 11.1 7–23
October 2011
Functional Description
Prefetchable Read Operations
All prefetchable PCI read requests that are claimed are initially retried.
The number of retried reads that can be remembered and passed on to the
Avalon-MM interface as read requests depends on the performance
profile selected in the PCI Compiler wizard. For burst transfers with
Single-Cycle Transfers Only performance profile, only one pending read
is handled at a time.
For Burst Transfers with Multiple Pending Reads, up to four delayed read
transactions can be in progress at the same time. The PCI-Avalon bridge
accepts up to four reads and forwards them to the interconnect. The reads
are completed in the order requested on the PCI bus.
If additional reads arrive after the maximum number of pending reads
are stored in the queue, the additional reads are retried and no
information is stored. After one of the pending reads is completed (or
discarded due to expiration of a timer), an additional read can be stored
in the queue and passed to the interconnect.
For every possible PCI-to-Avalon pending read request, there is a set of
registers that store the PCI memory address, command, and byte enables.
Therefore, the command can be matched on a subsequent retry. In
addition, there is dedicated PCI-to-Avalon read response buffer space
and buffer management logic for every possible pending read request.
PCI-to-Avalon command/write data buffer full, no data
transferred yet The target controller retries the operation on the PCI
bus. Nothing is remembered about the retried PCI write
operation. When the PCI write operation is
subsequently re-issued, it is treated as a new
operation.
PCI-to-Avalon command/write data buffer full, some
data transferred The target controller issues a disconnect on the PCI
bus. The current transaction is committed to the
PCI-to-Avalon command/write data buffer at its current
length. If and when the PCI write operation is
subsequently resumed, it is treated as a new operation.
Prefetchable target burst write with cacheline wrap
mode One data phase worth of data is transferred and the
request is disconnected.
Target abort Not applicable. The target controller will not terminate
a PCI write operation with a target abort.
Table 7–6. Termination of PCI Writes That Hit a Prefetchable BAR as a PCI Target (Part 2 of 2)
Termination Condition Resulting Action