Altera PCI Compiler - Manual (Page 212)

4–2 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Features
Features The PCI testbench includes the following features:
■ Easy to use simulation environment for any standard VHDL or
Verilog HDL simulator
■ Open source VHDL and Verilog HDL files
■ Flexible PCI bus functional model to verify your application that
uses any Altera PCI MegaCore function
■ Simulates all basic PCI transactions including memory read/write
operations, I/O read and write transactions, and configuration read
and write transactions
■ Simulates all abnormal PCI transaction terminations including target
retry, target disconnect, target abort, and master abort
■ Simulates PCI bus parking
■ Includes a simple reference design that performs basic memory and
I/O transactions
PCI Testbench
Files The Altera PCI testbench is included and installed with the PCI Compiler.
Figure 4–2 shows the directory structure of PCI testbench subdirectory,
where <path> is the directory in which the PCI Compiler is installed.
Figure 4–2. PCI Testbench Directory Structure
testbench
< HDL language>
< PCI MegaCore Function>
example
Contains files and scripts allowing you to simulate PCI
transactions
local_bfm
Contains a simple reference design
pci_top
Contains an IP functional simulation model
tb_src
Contains testbench source files
pci_compiler
< path>
megawizard_flow