Altera PCI Compiler - Manual (Page 23)

Altera Corporation User Guide Version 11.1 11
October 2011
About PCI Compiler
host bridge, Ethernet network adapter, and video card. The Altera PCI
MegaCore functions were tested on the Stratix EP1S25F1020C5 and
EP1S60F1020C6 devices. Hardware testing ensures that the PCI
MegaCore functions operate flawlessly under the most stringent
conditions.
During hardware testing with the Agilent E2928A PCI Bus Exerciser and
Analyzer, various tests were performed to guarantee robustness and
strict compliance. These tests included the following:
■ Memory read/write
■ I/O read/write
■ Configuration read/write
The tests generate random transaction types and parameters at the PCI
and local sides. The Agilent E2928A PCI Bus Exerciser and Analyzer
simulated random behavior on the PCI bus by randomizing transactions
with variable parameters such as the following:
■ Bus commands
■ Burst length
■ Data types
■ Wait states
■ Terminations
■ Error conditions
The local side also emulated a variety of test conditions in which the PCI
MegaCore functions experienced random wait states and terminations.
During the tests, the Agilent E2928A PCI Bus Exerciser and Analyzer also
acted as a PCI protocol and data integrity checker as well as a logic
analyzer to aid in debugging. This testing ensures that the functions
operate under the most stringent conditions in your system.
f
For more information on the Agilent E2928A PCI Bus Exerciser and
Analyzer, refer to the Agilent website at
www.agilent.com .
Performance
and Resource
Utilization This section lists the speed and approximate resource utilization of the
PCI MegaCore functions in supported Altera device families.
PCI Compiler with MegaWizard Plug-in Manager Flow
The speed and resource utilization estimates are based on a PCI
MegaCore function using one BAR that reserves 1 MByte of memory.
Implementing additional BARs generates additional logic in the PCI