Altera PCI Compiler - Manual (Page 284)

7–16 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
PCI Target Operation
PCI configuration read and write operations are automatically handled
by the PCI MegaCore function block of the PCI-Avalon bridge. The
functions provide access to all PCI configuration registers and behave
exactly as described in the PCI Compiler with MegaWizard flow section.
Refer to
“Configuration Read Transactions” on page 3–62 and
“Configuration Write Transactions” on page 3–76 .
1 When discussing PCI-Avalon bridge functionality, all PCI
memory write transactions are referred to as write and all PCI
memory read transactions are referred to as read. The specific
PCI command will be indicated only when the behavior of the
bridge is dependent on the actual PCI bus command.
Additionally, request and completion are used to describe
operations handled by the PCI-Avalon bridge. Request is used to
indicate that the command is being issued for the first time, and
completion is used to indicate that actual data is being
transferred. In a write operation, request and completion occur
within the same PCI transaction. However, in a read operation,
request and completion are usually two different transactions
separated by a significant amount of time.
The PCI-Avalon bridge has two distinct data paths: prefetchable and
non-prefetchable. Depending on the performance profile and type of
BARs used, a transaction is routed to one of the two data paths. If a
transaction hits a non-prefetchable BAR it will be handled by the
non-prefetchable data path. Additionally, if you select Single-Cycle
Transfers Only target performance profile, all PCI memory transactions
are routed to the non-prefetchable data path and the prefetchable data
path will be removed.
Transactions handled by a non-prefetchable data path have the following
key characteristics:
■ Are always handled as single data phase transactions
■ Read requests will be initially retried and completed as delayed read
operations
■ The requests will be directed to the Non-prefetchable Avalon-MM
master port. This path consists of single address and data registers,
and therefore, will have minimal latency. However, the path will not
support burst behavior.
Transactions that hit a prefetchable BAR will be routed to the
prefetchable data path and have the following characteristics:
■ Burst transactions are supported.