Altera PCI Compiler - Manual (Page 70)

2–12 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Variation File Parameters
8 CAP_LIST_ENA 0 Capabilities list enable. This bit determines if the
capabilities list will be enabled in the configuration
space. When this bit is set to 1, it sets the
capabilities list bit (bit 4) of the status register and
sets the capabilities register to the value of
CAP_PTR
.
9 CIS_PTR_ENA 0 CardBus CIS pointer enable. This bit enables the
CardBus CIS pointer register. When this bit is set
to 0, the function returns H"00000000" during a
configuration read to the CIS_PTR register.
10 INTERRUPT_ACK_ENA 0 Interrupt acknowledge enable. This bit enables
support for the interrupt-acknowledge command.
When set to 0, the function ignores the interrupt
acknowledge command. When set to 1, the
function responds to the interrupt acknowledge
command. The function treats the interrupt
acknowledge command as a regular target
memory read. The local side must implement the
necessary logic to respond to the interrupt
controller.
11 Reserved 0 Reserved.
12 INTERNAL_ARBITER_ENA (1) 0 This bit allows reqn and gntn to be used in
internal arbiter logic without requiring external
device pins. If the PCI MegaCore function and a
PCI bus arbiter are implemented in the same
device, the reqn signal should feed internal logic
and gntn should be driven by internal logic
without using actual device pins. If this bit is set to
1
, the tri-state buffer on the reqn signal is
removed, allowing an arbiter to be implemented
without using device pins for the reqn and gntn
signals.
Table 2–2. Bit Definition of the ENABLE_BITS Parameter (Part 2 of 5)
Bit
Number
Bit Name
Default
Value
Definition